Sachin Tolay articles - 15 total
Blocking vs Non-blocking vs Asynchronous I/O
When a program performs I/O → like reading from a file or socket → two key questions arise: Does...
Traditional IO vs mmap vs Direct IO: How Disk Access Really Works
In our earlier deep dive into Direct Memory Access (DMA), we explored how data can bypass the CPU to...
Understanding Direct Memory Access (DMA): How Data Moves Efficiently Between Storage and Memory
Transferring data between Storage and Memory can slow down a computer if the CPU has to manage every...
How HDDs and SSDs Store Data The Block Storage Model
When you open a file in your program, it seems like you can read or change any byte you want. But in...
Understanding OAuth 2.0 and OpenID Connect: A Step-by-Step Guide
If you’ve ever clicked “Sign in with Google” or “Connect with Facebook” on a website or app, you’ve...
Core Attributes of Distributed Systems: Reliability, Availability, Scalability, and More
Whether you’re building a simple web app or a large distributed system, users don’t just expect it to...
Memory Models Explained: How Threads Really See Memory
Modern processors and compilers aggressively reorder instructions to improve performance → a behavior...
Instruction Reordering: Your Code Doesn’t Always Run in the Order You Wrote It
When writing code, you naturally expect instructions to run one after the other in the exact order...
Superscalar vs SIMD vs Multicore: Understanding Modern CPU Parallelism
For many years, improving CPU performance meant increasing clock speed → allowing more cycles per...
CPU Pipelining: How Modern Processors Execute Instructions Faster
The key to modern processors’ speed lies in their ability to execute many instructions in parallel,...
Cache Coherence: How the MESI Protocol Keeps Multi-Core CPUs Consistent
Modern multi-core CPUs depend on caches to accelerate memory access and improve performance. However,...
Understanding CPU Cache Organization and Structure
Software performance is deeply influenced by how efficiently memory is accessed. The story behind...
Memory Access Demystified: How Virtual Memory, Caches, and DRAM Impact Performance
Modern software performance is deeply influenced by how efficiently memory is accessed. The full...
Understanding DRAM Internals: How Channels, Banks, and DRAM Access Patterns Impact Performance
Modern software performance depends heavily on how efficiently memory is accessed, and not just on...
Understanding DRAM Internals: How Channels, Banks, and DRAM Access Patterns Impact Performance
Modern software performance depends heavily on how efficiently memory is accessed, and not just on...