What Is Metastability?
Metastability occurs when a flip-flop receives input data that changes too close to the clock edge, violating setup or hold time. As a result, the output becomes unstable or unpredictable, potentially lasting for several clock cycles.

This is especially common when:

• Crossing clock domains (CDC)
• Asynchronous inputs are sampled directly

How to Handle Metastability in FPGA Designs
1. Use Synchronizer Flip-Flops

• Chain two (or more) flip-flops in series to "absorb" metastability.
• Allows the signal to stabilize before being used.

Example (Verilog):

verilog

reg sync_ff1, sync_ff2;

always @(posedge clk) begin
    sync_ff1 <= async_in;
    sync_ff2 <= sync_ff1;
end

wire stable_signal = sync_ff2;

Use two FFs minimum for asynchronous inputs. Some high-reliability designs use three.

2. Use Clock Domain Crossing (CDC) Techniques
a. Handshake Synchronization

• Use request/acknowledge signals with proper synchronization to transfer data safely.
• Useful for low-speed communication across domains.

b. Asynchronous FIFO

• Built-in dual-clock FIFOs allow safe data transfer between different clock domains.
• Available as IP cores in most FPGA toolchains (e.g., Xilinx, Intel/Altera).

c. Pulse Synchronization
Converts a single pulse into a "one-clock-wide" pulse in the destination clock domain using edge detection.

3. Use Constraints & FPGA Primitives
Declare synchronizers as "async_register" in constraints (e.g., XDC or SDC):

xdc

set_property ASYNC_REG TRUE [get_cells sync_ff1]

This tells the synthesis tool not to optimize away synchronization flip-flops.

4. Avoid Timing Violations

• Ensure sufficient setup and hold margins with proper constraints.
• Avoid long combinational paths feeding into synchronizers.

Best Practices